TLE5012_10 Datasheet, PDF (26/64 Pages) Infineon Technologies AG – GMR-Based Angular Sensor for Rotor-Position Sensing

TLE5012
Specifications
3.4.6 Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input CLK must fulfill certain requirements:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike filtered.
• The duty cycle factor should be 0.5 but can deviate to the values limited by t_{CLKh(f_min)} and t_{CLKl(f_min)}.
• The PLL is triggered at the positive edge of the clock; if more than 2 edges are missing, a chip reset is
generated automatically.
tCLKh
tCLK
tCLKl
Figure 14 External CLK timing definition
V_H
V_L
t
Table 11 CLK timing specification
Parameter
Symbol
Values
Unit
Min. Typ. Max.
Input frequency
CLK duty cycle¹⁾²⁾
f_CLK
3.8 4.0 4.2
CLK_DUTY 30
50
70
MHz
%
CLK rise time
t_CLKr
-
-
30
ns
CLK fall time
t_CLKf
-
-
30
ns
Digital clock
f_DIG
22.8 24 25.2
MHz
Internal oscillator frequency
f_CLK
3.8 4.0 4.2
MHz
1) Minimum Duty Cycle Factor: t_{CLKh(f_min)} / t_{CLK(f_min)} with t_{CLK(f_min)}= 1 / f_{CLK(f_min)}
2) Maximum Duty Cycle Factor: t_{CLKh(f_max)} / t_{CLK(f_min)} with t_{CLKh(f_max)}= t_{CLK(f_min)} - t_CLKl(min)
3) Not subject to production test - verified by design/characterization
Note / Test Condition
From V_L to V_H3)
From V_H to V_L3)
Final Data Sheet
26
V 1.0, 2010-11