TDA7200 Datasheet, PDF (26/49 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7200
Applications
from RSSI Gen
(ASK signal)
FSK PLL Demodulator
0.18 mV/kHz
typ. 2 V
1.5 V......2.5 V
ASK/FSK Switch
-
+ _ASK
+ FSK
-
R_{F3 int}
300k
R_{F4 int}
30k
ASK mode: v=1
FSK mode: v=11
R_{F1 int}
100k
MSEL
15
H=ASK
L=FSK
Data Filter
R_{F2 int}
100k
v=1
PEAK
DETECTOR
PDO
26
R_{T1 int} 56k
R_T2 390k
C15
100nF
Comp
-
+ _CP
25
+ CM
-
H=CP
L=CM
DATA Out
22
21
FFB
OOP
19
SLP
20
16
SLN
SSEL
C14
C12
R1
C13
Figure 9 ASK/FSK mode datapath
3.7
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above
(highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by
the external RC-combination. The upper cutoff frequency f3 is determined by the data
filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200µV/kHz. This gain is
increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic
gain of this circuit is 2.2mV/kHz within the bandpass. The gain for the DC content of FSK
signal remains at 200µV/kHz. The cut-off frequencies of the bandpass have to be chosen
such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the effect of the
drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at
the negative input of the slicer comparator (Pin20) is used. The comparator has no
hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the
comparator (i.e. 20nA) running over the external resistor R. This voltage raises the
voltage appearing at pin 20 (e.g. 1mV with R = 100kΩ). In order to obtain benefit of this
Data Sheet
26
V 1.0, 2007-05-02