TDA7200 Datasheet, PDF (16/49 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7200
Functional Description
2.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-
440MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of
approximately 21dB by utilising either high- or low-side injection of the local oscillator
signal. In case the mixer is interfaced only single-ended, the unused mixer input has to
be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner
frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance
of approximately 330Ω to facilitate interfacing the pin directly to a standard 10.7MHz
ceramic filter without additional matching circuitry.
2.4.3 PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain,
a phase detector with charge pump and a loop filter and is fully implemented on-chip.
The VCO is including spiral inductors and varactor diodes. The frequency range of the
VCO guaranteed over production spread and the specified temperature range is 820 to
860MHz. The oscillator signal is fed both to the synthesiser divider chain and to the
downconverting mixer. The VCO signal is divided by two before it is fed to the Mixer.
Depending on whether high- or low-side injection of the local oscillator is used, the
receiving frequency range is 400 to 420MHz and 420 to 440MHz - see also Section 3.4.
2.4.4 Crystal Oscillator
The calculation of the value of the necessary crystal load capacitance is shown in
Section 3.3, the crystal frequency calculation is explained in Section 3.4.
2.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of
approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It
has a typical input impedance of 330 Ω to allow for easy interfacing to a 10.7 MHz
ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
(RSSI) generator which produces a DC voltage that is directly proportional to the input
signal level as can be seen in Figure 4. This signal is used to demodulate ASK-
modulated receive signals in the subsequent baseband circuitry. The RSSI output is
applied to the modulation format switch, to the Peak Detector input and to the AGC
circuitry.
In order to demodulate ASK signals the MSEL pin has to be in its ‘High‘-state as
described in the next chapter.
Data Sheet
16
V 1.0, 2007-05-02