TDA7200 Datasheet, PDF (17/49 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7200
Functional Description
2.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is
contained fully on chip. The Limiter output differential signal is fed to the linear phase
detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain
is typically 200µV/kHz. The passive loop filter output that is comprised fully on chip is fed
to both the VCO and the modulation format switch described in more detail below. This
signal is representing the demodulated signal with low frequencies applied to the
demodulator demodulated to logic zero and high frequencies demodulated to logic ones.
However this is only valid in case the local oscillator is low-side injected to the mixer
which is applicable to receive frequencies above 420MHz. In case of receive frequencies
below 420MHz high frequencies are demodulated as logical zeroes due to a sign
inversion in the downconversion mixing process as the L0 is high-side injected to the
mixer. See also Section 3.4.
The modulation format switch is actually a switchable amplifier with an AC gain of 11 that
is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was
chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to
saturate the subsequent Data Filter wih the DC offset produced by the demodulator in
case of large frequency offsets of the IF signal. The resulting frequency characteristic
and details on the principle of operation of the switch are described in Section 3.6.
Table 3
MSEL Pin Operating States
MSEL
Open
Shorted to ground
Modulation Format
ASK
FSK
The demodulator circuit is switched off in case of reception of ASK signals.
2.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage
follower and two 100kΩ on-chip resistors. Along with two external capacitors a 2nd order
Sallen-Key low pass filter is formed. The selection of the capacitor values is described
in Section 3.2.
Data Sheet
17
V 1.0, 2007-05-02