TDA7200 Datasheet, PDF (18/49 Pages) Infineon Technologies AG – ASK/FSK Single Conversion Receiver

TDA7200
Functional Description
2.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a
maximum receive data rate of up to 100kBaud. The maximum achievable data rate also
depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs
are accessible. The output delivers a digital data signal (CMOS-like levels) for
subsequent circuits. A self-adjusting slicer-threshold on pin 20 its generated by a RC-
term. In ASK-mode alternatively a scaled value of the voltage at the PDO-output (approx.
87%) can be used as the slicer-threshold as shown in Table 4. The data slicer threshold
generation alternatives are described in more detail in Section 3.5.
Table 4
SSEL
X
High
Low
SSEL Pin Operating States
MSEL
Low
High
High
Selected Slicing Level (SL)
external SL on Pin 20 (RC-term, e.g.)
external SL on Pin 20 (RC-term, e.g.)
87% of PDO-output (approx.)
2.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the
receive data signal. A capacitor is necessary. The input is connected to the output of the
RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26). This output
can be used as an indicator for the received signal strength to use in wake-up circuits
and as a reference for the data slicer in ASK mode. Note that the RSSI level is also
output in case of FSK mode.
2.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the
device. A power down mode is available to switch off all subcircuits which is controlled
by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in
this case is typically 50nA.
Table 5
PDWN Pin Operating States
PDWN
Open or tied to ground
Tied to Vs
Operating State
Powerdown Mode
Receiver On
Data Sheet
18
V 1.0, 2007-05-02