TLE7181EM Datasheet, PDF (24/29 Pages) Infineon Technologies AG – H-Bridge and Dual Half Bridge Driver IC

H-Bridge and Dual Half Bridge Driver IC
TLE7181EM
Electrical Characteristics - Current sense signal conditioning (cont’d)
V_S = 7.0 to 36V, T_j = -40 to +150°C, gain = 5 to 75, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
5.3.10 High level output voltage of ISO V_OH
4.75 –
5.2
V
I_OH=-3mA
5.3.11
5.3.12
5.3.13
5.3.14
Output short circuit current
I_SCOP
Differential input resistance¹⁾
R_I
Common mode input capacitance¹⁾ C_CM
Common mode rejection ratio at
DC
C_MRR
CMRR =
20*Log((Vout_diff/Vin_diff) *
(Vin_CM/Vout_CM))
5
–
–
100 –
–
–
–
10
80
100 –
mA –
kΩ –
pF 10kHz
dB –
5.3.15 Common mode suppression²⁾ with C_MS
–
CMS = 20*Log(Vout_CM/Vin_CM)
Freq =100kHz
Freq = 1MHz
Freq = 10MHz
–
62
43
23
dB
V_IN=360mV*
sin(2*π*freq*t);
R_s=500Ω;
R_fb=7500Ω
5.3.16 Slew rate
d_V/dt
–
10
–
5.3.17 Large signal open loop voltage gain A_OL
(DC)
80
100 –
V/µs
dB
Gain≥ 5;
R_L=1.0kΩ;
C_L=500pF
–
5.3.18 Unity gain bandwidth¹⁾
G_BW
10
20
–
MHz R_L=1kΩ; C_L=100pF
5.3.19 Phase margin ¹⁾
F_M
–
50
–
°
Gain≥ 5;
R_L=1kΩ; C_L=100pF
5.3.20 Gain margin ¹⁾
A_M
–
12
–
dB
R_L=1kΩ; C_L=100pF
5.3.21 Bandwidth
B_WG
0.7
1.3
–
MHz
Gain=15;
R_L=1kΩ;
C_L=500pF;
R_s=500Ω
5.3.22 Output settle time to 98%
5.3.23 Output settle time to 98%¹⁾
t_set1
–
t_set2
–
1
1.8
µs
Gain=15;
R_L=1kΩ;
C_L=500pF;
0.3<V_ISO< 4.8V;
R_s=500Ω
4.6
–
µs Gain=75;
R_L=1kΩ;
C_L=500pF;
0.3<V_ISO< 4.8V;
R_s=500Ω
1) Not subjected to production test; specified by design
2) Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external
resistors.
Data Sheet
24
Rev 1.1, 2010-09-30