HYS64D16000GU-7-A Datasheet, PDF (24/30 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM-Modules

Table 11 SPD Codes for PC1600 Modules -8 (cont’d)
Byte#
Description
26
Access Time from Clock at not supported
CL = 1.5
27
Minimum Row Precharge 20 ns
Time
28
Minimum Row Act. to Row 15 ns
Act. Delay t_RRD
29
Minimum RAS to CAS Delay 20 ns
t_RCD
30
Minimum RAS Pulse Width 50 ns
t_RAS
31
Module Bank Density (per 128 MByte
Bank)
32
Addr. and Command Setup 1.1 ns
Time
33
Addr. and Command Hold 1.1 ns
Time
34
Data Input Setup Time
0.6 ns
35
Data Input Hold Time
0.6 ns
36 to 40 Superset Information
–
41
Minimum Core Cycle Time 70 ns
t_RC
42
Min. Auto Refresh Cmd 80 ns
Cycle Time t_FRC
43
Maximum Clock Cycle Time 12 ns
t_CK
44
Max. DQS-DQ Skew tDQSQ 0.6 ns
45
X-Factor tQHS
1.0 ns
46 to 61 Superset Information
–
62
SPD Revision
Revision 0.0
63
Checksum for Bytes 0 - 62 –
64
Manufactures JEDEC ID –
Codes
65 to 71 Manufactures
–
72
Module Assembly Location –
73 to 90 Module Part Number
–
91 to 92 Module Revision Code
–
93 to 94 Module Manufacturing Date –
95 to 98 Module Serial Number
–
99 to 127 –
–
128 to 255 open for Customer use
–
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
128MB
x64
1rank
–8
hex.
00
128MB
x72
1rank
–8
hex.
00
128MB
x64
2ranks
–8
hex.
00
128MB
x64
2ranks
–8
hex.
00
50
50
50
50
3C
3C
3C
3C
50
50
50
50
32
32
32
32
20
20
20
20
B0
B0
B0
B0
B0
B0
B0
B0
60
60
60
60
60
60
60
60
46
46
46
46
50
50
50
50
30
30
30
30
3C
3C
3C
3C
A0
A0
A0
A0
00
00
00
00
00
00
00
00
84
96
85
97
Infineon
–
–
–
–
–
–
–
Infineon
–
–
–
–
–
–
–
Infineon
–
–
–
–
–
–
–
Infineon
–
–
–
–
–
–
–
Data Sheet
24
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z