HYS64D16000GU-7-A Datasheet, PDF (23/30 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM-Modules

4
SPD Contents
HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
SPD Contents
Table 11
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SPD Codes for PC1600 Modules -8
Description
Number of SPD Bytes
128
Total Bytes in Serial PD
256
Memory Type
DDR-SDRAM
Number of Row Addresses 12
Number of Column
10
Addresses
Number of DIMM Banks
1/2
Module Data Width
×64/×72
Module Data Width (cont’d) 0
Module Interface Levels
SSTL_2.5
SDRAM Cycle Time at
8 ns
CL = 2.5
Access Time from Clock at 0.8 ns
CL = 2.5
DIMM config
non-ECC/ECC
Refresh Rate/Type
Self-Refresh 15.6 ms
SDRAM Width, Primary
×8
Error Checking SDRAM Data na/×8
Witdh
Minimum Clock Delay for
Back-to-Back Random
Column Address
t_CCD = 1 CLK
Burst Length Supported
2, 4 & 8
Number of SDRAM Banks 4
Supported CAS Latencies CAS latency = 2 & 2.5
CS Latencies
CS latency = 0
WE Latencies
Write latency = 1
SDRAM DIMM Module
Attributes
unbuffered
SDRAM Device Attributes: –
General
Min. Clock Cycle Time at
CAS Latency = 2
10 ns
Access Time from Clock for 0.8 ns
CL = 2
Minimum Clock Cycle Time not supported
for CL = 1.5
128MB
x64
1rank
–8
hex.
80
08
07
0C
0A
01
40
00
04
80
80
00
80
08
00
01
0E
04
0C
01
02
20
C0
A0
80
00
128MB
x72
1rank
–8
hex.
80
08
07
0C
0A
01
48
00
04
80
80
02
80
08
08
01
0E
04
0C
01
02
20
C0
A0
80
00
128MB
x64
2ranks
–8
hex.
80
08
07
0C
0A
02
40
00
04
80
80
00
80
08
00
01
0E
04
0C
01
02
20
C0
A0
80
00
128MB
x64
2ranks
–8
hex.
80
08
07
0C
0A
02
48
00
04
80
80
02
80
08
08
01
0E
04
0C
01
02
20
C0
A0
80
00
Data Sheet
23
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z