HYS64D16000GU-7-A Datasheet, PDF (21/30 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM-Modules

HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Electrical Characteristics
Table 10 AC Timing - Absolute Specifications –8/–7
Parameter
Symbol
–8
DDR200
Min. Max.
Address and control input hold time
t_IH
1.1 —
–7
DDR266A
Min. Max.
0.9
—
Unit Note/
Test Condition ¹⁾
ns fast slew rate
3)4)5)6)10)
1.1 —
1.0
—
ns slow slew rate
3)4)5)6)10)
Read preamble
Read preamble setup time
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
t_RPRE
t_RPRE1.5
t_RPRES
t_RPST
t_RAS
t_RC
0.9
0.9
1.5
0.40
50
70
1.1
1.1
—
0.60
120E+3
—
0.9
NA
NA
0.40
45
65
1.1
t_CK
t_CK
ns
0.60
t_CK
120E+3 ns
—
ns
Auto-refresh to Active/Auto-refresh
command period
t_RFC
80 —
75
—
ns
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
t_RCD
t_RP
t_RAP
t_RRD
20 —
20 —
20 —
15 —
20
—
ns
20
—
ns
20
—
ns
15
—
ns
Write recovery time
Auto precharge write recovery +
precharge time
t_WR
15 —
15
—
ns
t_DAL
(t_wr/t_CK) + (t_rp/t_CK)
t_CK
Internal write to read command delay t_WTR
1
—
t_WTR1.5 2
—
Exit self-refresh to non-read command t_XSNR 80 —
Exit self-refresh to read command
t_XSRD
200 —
Average Periodic Refresh Interval
t_REFI
— 7.8
1
—
t_CK
—
—
t_CK
75
—
ns
200
—
t_CK
—
7.8
µs
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V
2) Input slew rate ≥ 1 V/ns for DDR266, and = 1 V/ns for DDR200
CL > 1.5 ^2)3)4)5)
CL = 1.5 ^2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
CL > 1.5 ^2)3)4)5)
CL = 1.5 ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)14)
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
Data Sheet
21
Rev. 1.02, 2003-11