HYS64D16000GU-7-A Datasheet, PDF (10/30 Pages) Infineon Technologies AG – Unbuffered DDR SDRAM-Modules

HYS[64/72]D[16000/32020]GU-[7/8]-A
Unbuffered DDR SDRAM-Modules
Pin Configuration
Table 4 Pin Configuration (cont’d)
Frontside
PIN# Symbol
PIN# Symbol
40
DQ27
41
A2
85
V_DD
86
DQS7
42
V_SS
43
A1
87
DQ58
88
DQ59
44
NC / CB0
45
NC / CB1
89
V_SS
90
NC
46
V_DD
47
NC / DQS8
91
SDA
92
SCL
Backside
PIN# Symbol
132
V_SS
133 DQ31
134 NC / CB4
135 NC / CB5
136
V_DDQ
137 CK0
138
CK0
139
V_SS
PIN#
177
178
179
180
181
182
183
184
Symbol
DM7/DQS16
DQ62
DQ63
V_DDQ
SA0
SA1
SA2
V_DDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on ×64 organised non-ECC
modules.
Table 5
Density
128 MB
128 MB
256 MB
256 MB
Address Format
Organization Memory SDRAMs
Banks
16M × 64
1
16M × 72
1
32M × 64
2
32M × 72
2
16M × 8
16M × 8
16M × 8
16M × 8
# of
SDRAMs
8
9
16
18
# of
row/bank/
columns
bits
12/2/10
12/2/10
12/2/10
12/2/10
Refresh
4K
4K
4K
4K
Period Interval
64 ms
64 ms
64 ms
64 ms
15.6 µs
15.6 µs
15.6 µs
15.6 µs
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC modules.
A12 is used for 256 Mbit based modules only.
Data Sheet
10
Rev. 1.03, 2004-01
10292003-WLD7-IJ5Z