HYS64D32020GDL Datasheet, PDF (19/31 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Modules

HYS64D[1600x/32020]GDL–[5/6/7/8]–B
Small Outline DDR SDRAM Modules
AC Characteristics
Table 11 AC Timing - Absolute Specifications –6/–5 (cont’d)
Parameter
Symbol
–6
DDR333
Min. Max.
Address and control input setup time t_IS
0.75 —
–5
DDR400B
Min. Max.
0.6 —
Unit
ns
Note/ Test
Condition ¹⁾
fast slew rate
3)4)5)6)10)
0.8 —
0.7 —
ns
slow slew
rate
3)4)5)6)10)
Address and control input hold time t_IH
0.75 —
0.6 —
ns
fast slew rate
3)4)5)6)10)
0.8 —
0.7 —
ns
slow slew
rate
3)4)5)6)10)
Read preamble
t_RPRE
Read postamble
t_RPST
Active to Precharge command
t_RAS
Active to Active/Auto-refresh command t_RC
period
Auto-refresh to Active/Auto-refresh
command period
t_RFC
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B
command
t_RCD
t_RP
t_RAP
t_RRD
Write recovery time
t_WR
Auto precharge write recovery +
t_DAL
precharge time
Internal write to read command delay t_WTR
Exit self-refresh to non-read command t_XSNR
Exit self-refresh to read command
t_XSRD
Average Periodic Refresh Interval
t_REFI
0.9
0.40
42
60
1.1
0.9
0.60 0.40
70E+3 40
—
55
1.1
t_CK
0.60
t_CK
70E+3 ns
—
ns
72
—
65
—
ns
18
—
15
—
ns
18
—
15
—
ns
18
—
15
—
ns
12
—
10
—
ns
15
—
15
—
ns
t_CK
1
—
1
—
t_CK
75
—
75
—
ns
200 —
200 —
t_CK
—
7.8
—
7.8
µs
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
1) 0 ° C ≤T_A ≤70 ° C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t_DQSS.
Data Sheet
19
V1.2, 2003-08