ICE1CS02 Datasheet, PDF (17/27 Pages) Infineon Technologies AG – Combi PFC/ PWM Controller

Combi PFC/ PWM Controller
ICE1CS02
Functional Description
3.5.8
Leading Edge Blanking
V_Sense
V_csth
t_LEB = 220ns
3.5.10 External Synchronization
VREF=5V
external clock
10k
PWM
SYNC
V_sync
voltage at PWM SYNC
Synchronization
signal input
t
t_syncmax
R_duty
Max Duty
cycle
control
resistor
pwm_out
pfc_out
Figure 25 Leading Edge Blanking
Whenever MOS switch is switched on, a leading edge
spike is generated due to the primary-side
capacitances and the reverse recovery time of
secondary-side rectifier. This spike can cause the gate
drive to switch off unintentionally. In order to avoid a
premature termination of the switching pulse, this spike
is blanked.
3.5.9
Pre-short Protection
1.0V
Figure 27 External Synchronization and Max Duty
Selection
During External Synchronization, external clock is input
by the synchronization signal input. PFC output is kept
in synchronization with PWM output in 1:2 ratio. The
maximum allowable external sync pulse width off time
is 0.5µs.
3.5.11
Max Duty Cycle Selection
Vsync (V)
> 3.0 < 3.0
Vsense (V)
- > 2.6 < 2.6
CS
GATE
3.8V
Vpreshort
PROTECT
Max Duty
Cycle (%)
47 47 60
Figure 28 Max Duty Cycle Selection Table
The maximum duty cycle is selected based on the
above setting at the PFC Vsense and PWM SYNC
pins.
3.5.12 PWM Slope Compensation
Figure 26 Pre-short Protection
The IC will enter into protection, turning off the gate
when voltage at pin 9 (PWM CS) exceed 1.0V for a
period set externally through pin 11 (PWM Pre-short).
The IC will be resetted when IC exit out of PWM BOP.
Iramp
PWMout
Vsync
>3.0V = OFF
<3.0V = ON
PWM CS
Rgate
CoolMOS _{PWM CS}
Islope
Rsl_comp
Rsl_comp Rcs
variable to
change slope
for
compensation
V_Rcs
PWMout
gnd
Figure 29 PWM slope compensation
The IC will enter into slope compensation at PWM CS
pin when Vsync is less than 3.0V.
Version 1.0
17
25 July 2008