ICE1CS02 Datasheet, PDF (10/27 Pages) Infineon Technologies AG – Combi PFC/ PWM Controller

Combi PFC/ PWM Controller
ICE1CS02
Functional Description
3.4 PFC Section
The IC operates with a cascaded control; the inner
current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for
the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to
determine the corresponding input current. This means
the average input current follows the input voltage as
long as the device operates in CCM. Under light load
condition, depending on the choke inductance, the
system may enter into discontinuous conduction mode
(DCM). In DCM, the average current waveform will be
distorted but the resultant harmonics are still low
enough to meet the Class D requirement of IEC 1000-
3-2.
The outer voltage loop controls the output bus voltage.
Depending on the load condition, OTA1 establishes an
appropriate voltage at VCOMP pin which controls the
amplitude of the average input current.
The IC is equipped with various protection features to
ensure safe operating condition for both the system
and device. Important protection features are namely
Brown-out protection, Current Limitation and Output
Under-voltage Protection.
3.4.1
Power Supply
An internal under voltage lockout (UVLO) block
monitors the VCC power supply. As soon as it exceeds
12V and the voltage at pin 2 (PFC VSENSE) is >0.6V,
the IC begins operating its gate drive and performs its
Startup as shown in Figure 5.
.
V_VSENSE > 0.6 V V_VSENSE < 0.6 V
V_VSENSE > 0.6 V
V_CC
12 V
11 V
t
IC's
State
OFF
Start Normal
Up Operation
Open loop/
Standby
Normal
Operation
OFF
ground via switch S1 during UVLO and other fault
conditions (see later section on “System Protection”).
During power up when V_OUT is less than 83% of the
rated level, it sources a constant 30µA into the
compensation network at VCOMP pin, causing the
voltage at this pin to rise linearly. This results in a
controlled linear increase of the input current from 0A
thus reducing the stress on the external component.
When V_OUT is within 83% and 95% of the rated value,
VCOMP voltage is level-shifted by the Enhance
Dynamic Response function, to ensure there is no long
period of low or no current.
When V_OUT approaches its rated value, OTA1’s
sourcing current drops and so does the level shift of the
window detect block. The normal voltage loop then
takes control.
VSENSE
R4
( _{R3 + R4} x V_OUT )
VCOMP
OTA1
3V
S1
protect
R6
C4
C5
Figure 6 Start-up
3.4.3
System Protection
The IC provides several protection features in order to
ensure the PFC system in safe operating range.
Depending on the input line voltage (V_IN) and output
bus voltage (V_OUT), Figure 7 and 8 show the conditions
when these protections are active.
Figure 5 State of Operation respect to VCC
If VCC drops below 11V, the IC is off. The IC will then
be consuming typically 1.3mA. The IC can be turned off
and forced into standby mode by pulling down the
voltage at pin 2 (PFC VSENSE) to lower than 0.6V.
3.4.2
Start-up
Figure 6 shows the operation of voltage loop’s OTA1
during startup. The VCOMP pin is pull internally to
Version 1.0
10
25 July 2008