ICE1CS02 Datasheet, PDF (14/27 Pages) Infineon Technologies AG – Combi PFC/ PWM Controller

Combi PFC/ PWM Controller
ICE1CS02
Functional Description
From
L1
Full-wave
Retifier
R7
D1
R3 ^Vout
C2
R4
PWM Logic
HIGH to
turn on
VCC
Gate Driver
LV
Z1
External
MOS
Current Loop
+
PWM Generation
V_IN
Gate Driver
GATE
* LV: Level Shift
GATE
Av(I_IN)
Nonlinear
Gain
t
OTA1
3V
VSENSE
Figure 17 Gate Driver
VCOMP
R6
C4
C5
3.5
3.5.1
PWM Section
Startup Phase
Soft Start counter
Soft Start
Figure 16 Voltage Loop
3.4.15 Enhanced Dynamic Response
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage V_VSENSE at pin 2 (PFC VSENSE).
Whenever V_VSENSE exceeds the reference value (3V)
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of V_OUT.
SoftS
Soft Start
Soft-Start
Comparator
C7
&
G8
Gate Driver
3.4.16 Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 18) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 6 (PFC OUT) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the
gate drive is internally pull low to maintain the off state.
0.6V
0.4V
x3.2
CS
PWM OP
Figure 18 Soft Start
In the Startup Phase, the IC provides a Soft Start
period to control the maximum primary current by
means of a duty cycle limitation. The Soft start function
Version 1.0
14
25 July 2008