ICE1CS02 Datasheet, PDF (12/27 Pages) Infineon Technologies AG – Combi PFC/ PWM Controller

Combi PFC/ PWM Controller
ICE1CS02
Functional Description
Full-wave
Current Limit
Rectifier
ISENSE
1.0V
C2
R2
I_INDUCTOR
R1
1.43x
OP1
Turn Off
Driver
Figure 11 Peak Current Limit (PCL)
3.4.6
Open Loop Protection / Input Under
Voltage Protect (OLP)
Whenever VSENSE voltage falls below 0.6V, or
equivalently V_OUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V_IN for
normal operation. In this case, most of the blocks within
the IC will be shutdown. It is implemented using
comparator C3 with a threshold of 0.6V as shown in the
IC block diagram in Figure 2.
3.4.7
Over-Voltage Protection (OVP)
Whenever V_OUT exceeds the value set by pin 3 (PFC
OVP), higher than 3.15V, the over-voltage protection
OVP is active as shown in Figure 8, turning off gate. In
addition, a VSENSE voltage higher than 3.15V will
immediately reduce the output duty cycle, bypassing
the normal voltage loop control. This results in a lower
input power to reduce the output voltage V_OUT.
3.4.8
Complete Current Loop
The complete system current loop is shown in Figure
13.
From
Full-wave
Retifier
L1
R7
R2
R1
PFC
ISENSE
Current Loop
PFC
ICOMP
C3
Current Loop
Compensation
OTA2
1.0mS
+/-50uA (linear range)
S2
4V
Fault
D1
R3 ^Vout
C2
R4
GATE
voltage
proportional to
averaged
Inductor current
PWM
Comparator
C1
Gate
Driver
RQ
S
PWM Logic
Nonlinear
Gain
Input From
Voltage Loop
Figure 12 Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin 16 (PFC ISENSE), resulted from the
inductor current flowing across R1. The averaged
waveform is compared with an internal ramp in the
ramp generator and PWM block. Once the ramp
crosses the average waveform, the comparator C1
turns on the driver stage through the PWM logic block.
The Nonlinear Gain block defines the amplitude of the
inductor current. The following sections describe the
functionality of each individual blocks.
3.4.9
Current Loop Compensation
The compensation of the current loop is done at the pin
1 (PFC ICOMP). This is the OTA2 output and a
capacitor C3 has to be installed at this node to ground
(see Figure 13). Under normal mode of operation, this
pin gives a voltage which is proportional to the
averaged inductor current. This pin is internally shorted
to 4V in the event of IC shuts down when OLP and
UVLO occur.
3.4.10 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D_OFF for a
CCM PFC system is given as
D_OFF
=
---V----^I--^N----
V_OUT
From the above equation, D_OFF is proportional to V_IN.
Version 1.0
12
25 July 2008