ICE1CS02 Datasheet, PDF (16/27 Pages) Infineon Technologies AG – Combi PFC/ PWM Controller

If Vout is 330V, the duty cycle will be set back to
0.47.The switching frequency is set to f_switch = 130kHz.
3.5.4
PWM-Latch FF1
The output of the oscillator clock will provide
continuous pulse to the PWM-Latch which would turn
on the external MOS switch. After the PWM-Latch is
set, it can be reset by the PWM comparator, the Soft
Start comparator or the Current-Limit comparator.
When it is in reset mode, the output of the driver is
down immediately.
3.5.5
PWM Brown out
Combi PFC/ PWM Controller
ICE1CS02
Functional Description
PWM Logic
HIGH to
turn on
VCC
Gate Driver
LV
Z1
* LV: Level Shift
External
MOS
GATE
1.95V
C11
PFC
VSENSE
C12
2.85V
Blanking Time
50us ^{R Q}
SQ
Figure 22 PWM brown out circuit
Figure 23 Gate Driver
3.5.7
Current Limiting
PWM Latch
FF1
C10
PWM-OP
V_csth
Leading
Edge
Blanking
220ns
The voltage of the bus voltage is sensed through the
pin 2 (PFC VSENSE). When V_SENSE drops to lower than
1.95V, the gate signal will stop. When the V_SENSE rises
to higher than 2.85V, gate signal will resume again with
soft-start (see Figure 23). The blanking time of 50us is
added in order to avoid the noise interruption.
10kΩ
1pF
D1
PWM CS
3.5.6
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 23) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (PWM OUT) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the
gate drive is internally pull low to maintain the off state.
Figure 24 Current Limiting
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the MOS switch is sensed via an
external sense resistor R_Sense. By means of R_Sense the
source current is transformed to a voltage V_{cur_sense}
which is fed into the PWM CS pin. If this voltage
exceeds the internal threshold voltage V_csth the
comparator C10 immediately turns off the gate drive by
resetting
the
PWM
Latch
FF1.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated into the current sense path
before connecting to the PWM-OP.
Version 1.0
16
25 July 2008