ICS87974I Datasheet, PDF (9/16 Pages) Integrated Device Technology – Fully integrated PLL

ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The ICS87974I
provides separate power supplies to isolate any high
switching noise from the outputs to the internal PLL. V_DD,
V_DDA, and V_DDOx should be individually connected to the
power supply plane through vias, and bypass capacitors
should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each V_DDA pin.
The 10Ω resistor can also be replaced by a ferrite bead.
V
DD
V
DDA
3.3V
.01μF 10Ω
.01μF
10 μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
87974CYI
www.idt.com
9
REV. E JULY 26, 2010