ICS87974I Datasheet, PDF (7/16 Pages) Integrated Device Technology – Fully integrated PLL

ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5. AC CHARACTERISTICS,
V_DD
=
V_DDA
=
V
DDOX
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Qx ÷ 2, VCO ÷ 2
125
f_MAX
Output Frequency
Qx ÷ 4, VCO ÷ 2
63
Qx ÷ 6, VCO ÷ 2
42
f_VCO
PLL VCO Lock Range; NOTE 5
200
500
t_PD
SYNC to Feedback
Propagation Delay; NOTE 2, 5
PLL_SEL = 3.3V,
fREF = 50MHz
-250
100
tsk(o)
tjit(cc)
Output Skew; NOTE 4, 5
Cycle-to-Cycle Jitter;
NOTE 5, 6
Measured on rising
edge at V_DDO/2
350
±100
t_L
PLL Lock Time
10
t_R / t_F
Output Rise/Fall Time
0.8V to 2.0V
0.15
1.5
t_PW
Output Pulse Width
t_Period/2 - 800 t_Period/2 ± 500 t_Period/2 + 800
t_EN
Output Enable Time
2
10
t_DIS
Output Disable Time
2
10
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the V_DD/2 point of the input to theV_DDOx/2 of the output.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOx/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Measured as peak-to-peak.
Units
MHz
MHz
MHz
MHz
ps
ps
ps
mS
ns
ps
ns
ns
87974CYI
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7
REV. E JULY 26, 2010