ICS87974I Datasheet, PDF (4/16 Pages) Integrated Device Technology – Fully integrated PLL

ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 15, 19,
24, 30, 35, 39,
43, 47, 51
2
Name
GND
nMR/OE
3
CLK_EN
4
SEL_B
5
SEL_C
6
PLL_SEL
7
SEL_A
8
CLK_SEL
Type
Description
Power
Power supply ground.
Input
Input
Input
Input
Input
Input
Input
Pullup
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Active High Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are tri-
stated (HiZ). When logic LOW, the internal dividers and dividers
and the outputs are enabled. LVCMOS / LVTTL interface levels.
Synchronizing clock enable. When HIGH, clock outputs QAx:QCx
are enabled. When LOW, clock outputs QAx:QCx are low.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects between the PLL and the reference clock as the input to
the dividers. When HIGH, selects PLL. When LOW, selects the
reference clock. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
9
CLK0
Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
10
CLK1
Input Pullup Reference clock input. LVCMOS / LVTTL interface levels.
11, 27, 42
nc
Unused
No connect.
12
13
14, 20
16, 18,
21, 23, 25
V_DD
V_DDA
FB_SEL0,
FB_SEL1
QA4, QA3,
QA2, QA1, QA0
Power
Power
Input
Output
Core supply pin.
Analog supply pin.
Pulldown
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
17, 22, 26
28
29
V_DDOA
V_DDOFB
QFB
Power
Power
Output
Output supply pins for Bank A clock outputs.
Output supply pin for QFB clock output.
Clock output. LVCMOS / LVTTL interface levels.
31
32, 34,
36, 38, 40
33, 37, 41
44, 46,
48, 50
45, 49
52
FB_IN
QB4, QB3,
QB2, QB1, QB0
V_DDOB
QC3, QC2,
QC1, QC0
V_DDOC
VCO_SEL
Input
Output
Power
Output
Power
Input
Pullup
Pulldown
Feedback input to phase detector for generating clocks with
"zero delay". Connect to pin 29.
LVCMOS / LVTTL interface levels.
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank B clock outputs.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank C clock outputs.
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87974CYI
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4
REV. E JULY 26, 2010