ICS87974I Datasheet, PDF (10/16 Pages) Integrated Device Technology – Fully integrated PLL

ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS87974I layout example used in this
layout guideline is shown in Figure 2A. The ICS87974I rec-
ommended PCB board layout for this example is shown in
Figure 2B. This layout example is used as a general guide-
line. The layout in the actual system will depend on the se-
lected component types, the density of the components, the
density of the traces, and the stack up of the P.C. board.
VDDO
Zo = 50
R8
43
Receiver
Reset
pulse or
nMR
CLK_EN
3.3V
pull up
SELB
SELC
Q1
PLL_SEL
RS
Zo = 50 Ohm
SELA
CLK_SEL
3.3V LVCMOS Driver
R7
VDD
10
C16
10u
C11
0.01u
VDD
VDD
C13
0.01u
RU2
1K
RU3
1K
RU4
SP
RU5
SP
RU6
SP
RU7
SP
CLK_EN
PLL_SEL
SELA
SELB
SELC
CLK_SEL
U3
1
2
3
4
5
6
GND
nMR
CLK_EN
SELB
SELC
7
8
9
PLL_SEL
SELA
CLK_SEL
10
11
12
13
CLK0
CLK1
nc
VDD
VDDA
87974
GND
QB1
VDDOB
QB2
GND
39
38
37
36
35
34
QB3
VDDOB
QB4
33
32
31
FB_IN
GND
QFB
VDDOFB
nc
30
29
28
27
Zo = 50
R5
43
Receiver
Zo = 50
R3
43
Zo = 50
R1
43
Receiver
Receiver
RD2
SP
RD3
SP
RD4
1K
RD5
1K
RD6
1K
RD7
1K
SP = Space (i.e. not intstalled)
Example of Reconfigurable Logic Control Input
(U1-17) VDDO
C3
0.1uF
(U1-22) (U1-26) (U1-28) (U1-33) (U1-37) (U1-41) (U1-45) (U1-49)
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C12
0.1uF
FIGURE 2A. ICS87974I LVCMOS/LVTTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
87974CYI
www.idt.com
10
REV. E JULY 26, 2010