ICS87974I Datasheet, PDF (1/16 Pages) Integrated Device Technology – Fully integrated PLL

ICS87974I
LOW SKEW, 1-TO-15,
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87974I is a low skew, low jitter 1-to-15 LVCMOS/
LVTTL Clock Generator/Zero Delay Buffer. The device has
a fully integrated PLL and three banks whose divider ratios
can be independently controlled, providing output
frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In
addition, the external feedback connection provides for a
wide selection of output-to-input frequency ratios. The CLK0
and CLK1 pins allow for redundant clocking on the input
and dynamically switching the PLL between two clock
sources.
Guaranteed low jitter and output skew characteristics make
the ICS87974I ideal for those applications demanding well
defined performance and repeatability.
FEATURES
• Fully integrated PLL
• Fifteen single ended 3.3V LVCMOS/LVTTL outputs
• Two LVCMOS/LVTTL clock inputs for redundant clock
applications
• CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 350ps (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
GND
nMR/OE
CLK_EN
SEL_B
SEL_C
PLL_SEL
SEL_A
CLK_SEL
CLK0
CLK1
nc
VDD
VDDA
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
ICS87974I
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
GND
QB1
VDDOB
QB2
GND
QB3
VDDOB
QB4
FB_IN
GND
QFB
VDDOFB
nc
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87974CYI
www.idt.com
1
REV. E JULY 26, 2010