ICS854S006I Datasheet, PDF (9/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both differential signals must meet
the V and V input requirements. Figures 2A to 2F show interface
PP
CMR
examples for the CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in Figure
2A, the input termination applies for IDT open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
3.3V
R1
R2
50
50
CLK
nCLK
Differential
Input
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50
50
nCLK
Differential
Input
R2
50
FIGURE 2A. CLK/nCLK INPUT DRIVEN BY AN
IDT OPEN EMITTER LVHSTL DRIVER
FIGURE 2B. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
Differential
R1
R2
84
84
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Receiver
FIGURE 2C. CLK/nCLK INPUT DRIVEN BY A
3.3V LVPECL DRIVER
FIGURE 2D. CLK/nCLK INPUT DRIVEN BY A
3.3V LVDS DRIVER
2.5V
*R3 33
Zo = 50Ω
Zo = 50Ω
*R4 33
HCSL
R1
50
*Optional – R3 and R4 can be 0Ω
3.3V
CLK
nCLK
Differential
R2
Input
50
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
CLK
R1
R2
120
120
nCLK
Differential
Input
FIGURE 2E. CLK/nCLK INPUT DRIVEN BY A
3.3V HCSL DRIVER
FIGURE 2F. CLK/nCLK INPUT DRIVEN BY A
2.5V SSTL DRIVER
ICS854S006AGI REVISION B JANUARY 18, 2010
9
©2010 Integrated Device Technology, Inc.