ICS854S006I Datasheet, PDF (1/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

Low Skew, 1-to-6, Differential-to-
LVDS Fanout Buffer
ICS854S006I
DATA SHEET
GENERAL DESCRIPTION
The ICS854S006I is a low skew, high perfor-
ICS
mance 1-to-6 Differential-to-LVDS Fanout Buffer.
HiPerClockS™ _{The CLK, nCLK pair can accept most standard dif-}
ferential input levels. The ICS854S006I is charac-
terized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output skew characteristic s
make the ICS854S006I ideal for those clock distribution
applications demanding well defined performance and
r e p e a t a b i l i t y.
FEATURES
• Six differential LVDS outputs
• One differential clock input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 1.7GHz
• Translates any single ended input signal to LVDS levels
with resistor bias on nCLK input
• Output skew: 55ps (maximum)
• Propagation delay: 850ps (maximum)
• Additive phase jitter, RMS: 0.067ps (typical)
• Full 3.3V or 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK ^Pullup
nCLK ^Pulldown
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
PIN ASSIGNMENT
nCLK 1
CLK 2
VDD 3
VDDO 4
Q0 5
nQ0 ⁶
GND ⁷
Q1 8
nQ1 ⁹
VDDO ¹⁰
Q2 ¹¹
nQ2 ¹²
24 GND
23 GND
22 VDD
21 VDDO
20 nQ5
19 Q5
18 GND
17 nQ4
16 _Q4
15 _VDDO
14 _nQ3
13 _Q3
ICS854S006I
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
ICS854S006AGI REVISION B JANUARY 18, 2010
1
©2010 Integrated Device Technology, Inc.