ICS854S006I Datasheet, PDF (4/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4D. LVDS DC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Differential Output Voltage
326
Δ V_OD
V_OD Magnitude Change
V_OS
Offset Voltage
1.28
Δ V_OS
V_OS Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
Typical
Maximum
526
50
1.44
50
Units
mV
mV
V
mV
TABLE 4E. LVDS DC CHARACTERISTICS, V_DD = V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Differential Output Voltage
305
Δ V_OD
V_OD Magnitude Change
V
Offset Voltage
1.1
OS
Δ V_OS
V_OS Magnitude Change
NOTE: Please refer to Parameter Measurement Information for output information.
NOTE: Maximum value is a design target spec.
Typical
Maximum
505
50
1.45
50
Units
mV
mV
V
mV
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
1.7
GHz
300
850
ps
55
ps
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
622.08MHz,
Integration Range: 12kHz – 20MHz
0.067
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
50
≤ 1.2GHz
47
250
ps
53
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
tjit
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
622.08MHz,
Integration Range: 12kHz – 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
For NOTES, see Table 5A.
20% to 80%
≤ 1.2GHz
Minimum Typical
300
0.067
50
47
Maximum Units
1.7
GHz
800
ps
55
ps
ps
250
ps
53
%
ICS854S006AGI REVISION B JANUARY 18, 2010
4
©2010 Integrated Device Technology, Inc.