ICS854S006I Datasheet, PDF (2/15 Pages) Integrated Device Technology – Low Skew, 1-to-6, Differential-to - LVDS Fanout Buffer One differential clock input pair

ICS854S006I Data Sheet
LOW SKEW, 1-TO-6, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
nCLK
Input Pulldown Inverting differential clock input.
2
CLK
Input
Pullup Non-inverting differential clock input.
3, 22
4, 10, 15, 21
5, 6
V_DD
V_DDO
Q0, nQ0
Power
Power
Output
Positive supply pins.
Output supply pins.
Differential output pair. LVDS interface levels.
7, 18, 23, 24
GND
Power
Power supply ground.
8, 9
Q1, nQ1
Output
Differential output pair. LVDS interface levels.
11, 12
Q2, nQ2
Output
Differential output pair. LVDS interface levels.
13, 14
Q3, nQ3
Output
Differential output pair. LVDS interface levels.
16, 17
Q4, nQ4
Output
Differential output pair. LVDS interface levels.
19, 20
Q5, nQ5
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
CLK
nCLK
Outputs
Q0:Q5
nQ0:nQ5
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
ICS854S006AGI REVISION B JANUARY 18, 2010
2
©2010 Integrated Device Technology, Inc.