82V3155 Datasheet, PDF (9/34 Pages) Integrated Device Technology – ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Name
TRST
TCK
TMS
IC0, IC2
Type
Pin Number
Description
Test Reset.
I
30
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally
pulled up to V_DDD. It is connected to the ground for normal applications.
I
28
Test Clock.
Provides the clock for the JTAG test logic.
Test Mode Select.
I
31
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V_DDD.
-
53, 55 These pins should be connected to V_SS.
Pin Description
9
January 11, 2017