82V3155 Datasheet, PDF (14/34 Pages) Integrated Device Technology – ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

82V3155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
2.7
DPLL BLOCK
As shown in Figure - 7, the DPLL Block consists of a Phase Detector,
a Limiter, a Loop Filter, a Digital Control Oscillator and Divider.
Limiter circuit for phase slope control.
In the Freerun or Holdover mode, the Frequency Select Circuit, the
Phase Detector and the Limiter are inactive, and the input reference
signal is not used.
2.7.1
PHASE DETECTOR (PHD)
In the Normal mode, the Phase Detector compares the virtual
reference signal from the TIE Control Circuit with the feedback signal
from the Frequency Select Circuit, and outputs an error signal
corresponding to the phase difference. This error signal is sent to the
2.7.2
LIMITER
The Limiter is used to limit the phase slope. It ensures that the
maximum output phase slope is limited to 5 ns per 125 µs for all input
transient conditions. This well meets the AT&T TR62411 and Telcordia
Fraction_C19
Fraction_T1
Fraction_C6
Output Interface
19.44 MHz
155.52 MHz
APLL
C19_Divider
24.704 MHz
T1_Divider
32.768 MHz
E1_Divider
25.248 MHz
C6_Divider
Fx_sel1 Fx_sel0 (x = 0 or 1)
C2/C1.5
C155POS
C155NEG
C19o
F19o
C1.5o
C3o
C2o
C4o
C8o
C16o
C32o
F0o
F8o
F16o
F32o
RSP
TSP
C6o
Loop Filter
Limiter
Phase ^{Feedback Signal}
Detector
Frequency
Selection
Circuit 1
FLOCK
Virtual Reference IN_sel F1_sel1 F1_sel0
Figure - 7 DPLL Block Diagram
In the Normal mode, the Limiter receives the error signal from the
Phase Detector, limits the phase slope within 5 ns per 125 µs and sends
the limited signal to the Loop Filter.
In the Fast Lock mode, the Limiter is disabled, and the DPLL locks to
the input reference within 500 ms, which is much shorter than that in the
Normal mode.
Frequency
Selection
Circuit 0
F0_sel1 F0_sel0
Functional Description
14
January 11, 2017