82V3155 Datasheet, PDF (6/34 Pages) Integrated Device Technology – ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

List of Figures
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82V3155 56-pin SSOP Package Pin Assignment ......................................................................................................................... 2
State Control Circuit .......................................................................................................................................................................... 10
State Control Diagram....................................................................................................................................................................... 10
TIE Control Block Diagram................................................................................................................................................................ 12
Reference Switch with TIE Control Block Enabled............................................................................................................................ 13
Reference Switch with TIE Control Block Disabled........................................................................................................................... 13
DPLL Block Diagram ......................................................................................................................................................................... 14
Clock Oscillator Circuit ...................................................................................................................................................................... 16
Power-Up Reset Circuit..................................................................................................................................................................... 16
82V3155 Power Decoupling Scheme.......................................................................................................................................... 17
Timing Parameter Measurement Voltage Levels .............................................................................................................................. 29
Input to Output Timing (Normal Mode).............................................................................................................................................. 31
Output Timing 1................................................................................................................................................................................. 32
Output Timing 2................................................................................................................................................................................. 33
Input Control Setup and Hold Timing ................................................................................................................................................ 33
List of Figures
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January 11, 2017