82V3155 Datasheet, PDF (32/34 Pages) Integrated Device Technology – ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

82V3155
F8o
F0o
F16o
F32o
C32o
C16o
C8o
C4o
C2o
(see Note 1)
C6o
C3o
C1.5o
(see Note 1)
F19o
C19o
C155
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
t_F0WL
t_F8WH
t_F0D
t_C32WH
t_C16W
t_C8W
t_C8W
t_F16WL
t_F16S
t_F32WL
t_F32S
t_F16D
t_F16H
t_F32D
t_F32H
t_C32D
t_C16D
t_C8D
t_C4W
t_C4W
t_C4D
t_C2W
t_C2D
t_C6W
t_C6W
t_C6D
t_C3W
t_C3D
t_C15W
t_F19WH
t_C15D
t_F19D
t_C19W
t_F19S
t_F19H
t_C19D
t_C155W
t_C155D
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_T
V_DD
0
Figure - 13 Output Timing 1
Timing Characteristics
32
January 11, 2017