82V3155 Datasheet, PDF (30/34 Pages) Integrated Device Technology – ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS

82V3155
Parameter
Description
t_C8D F8o to C8o delay
t_C16D F8o to C16o delay
t_C19D F8o to C19o delay
t_C32D F8o to C32o delay
t_C155D F8o to C155 delay
t_TSPD F8o to TSP delay
t_RSPD F8o to RSP delay
t_C15W
t_C3W
C1.5o pulse width high or low
C3o pulse width high or low
t_C6W C6o pulse width high or low
t_C2W C2o pulse width high or low
t_C4W C4o pulse width high or low
t_C8W C8o pulse width high or low
t_C16W C16o pulse width high or low
t_C19W
t_C32WH
C19o pulse width high or low
C32o pulse width high
t_C155W C155 pulse width high or low
t_TSPW TSP pulse width high
t_RSPW RSP pulse width high
t_F0WL F0o pulse width low
t_F8WH
t_F16WL
F8o pulse width high
F16o pulse width low
t_F19WH F19o pulse width high
t_0RF Output clock and frame pulse rise or fall time
t_S Input controls setup Time
t_H Input controls hold Time
t_F16D F8o to F16o delay
t_F19D F8o to F19o delay
t_F32D F8o to F32o delay
t_F32S F32o setup to C32o falling
t_F32H
t_F32WL
F32o hold to C32o falling
F32o pulse width low
ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Min.
Typ.
Max.
-2
0
+2
-2
0
+2
-8
0
+8
-2
2
+2
-3
0
+3
-3
0
+3
-3
0
+3
323
161
82
244
122
61
30.5
25
14.4
3.25
486
490
243
123.6
60.9
25
3
100
100
27.1
30.1
33.1
17
25
33
12
15.8
19
11
11
30.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
Timing Characteristics
30
January 11, 2017