7130SA55P Datasheet, PDF (9/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE⁽⁷⁾⁸M824S258M824S30 7132158M824S4
7130X20⁽¹⁾ 7130X25⁽⁹⁾ 7130X35 7130X55 7130X100
7140X25⁽⁹⁾ 7140X35 7140X55 7140X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Busy Timing (For Master lDT7130 Only)
tBAA BUSY Access Time from Address
tBDA BUSY Disable Time from Address
tBAC BUSY Access Time from Chip Enable
tBDC BUSY Disable Time from Chip Enable
tWH Write Hold After BUSY⁽⁶⁾
tWDD Write Pulse to Data Delay⁽²⁾
tDDD Write Data Valid to Read Data Delay⁽²⁾
tAPS Arbitration Priority Set-up Time⁽³⁾
tBDD BUSY Disable to Valid Data⁽⁴⁾
Busy Timing (For Slave IDT7140 Only)e
tWB Write to BUSY Input⁽⁵⁾
tWH Write Hold After BUSY⁽⁶⁾
tWDD Write Pulse to Data Delay⁽²⁾
tDDD Write Data Valid to Read Data Delay⁽²⁾
— 20 — 20 — 20 — 30 — 50
ns
— 20 — 20 — 20 — 30 — 50 ns
— 20 — 20 — 20 — 30 — 50
ns
— 20 — 20 — 20 — 30 — 50 ns
12 — 15 — 20 — 20 — 20 —
ns
— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns
5—
5—
5 — 5—5 —
ns
— 25 — 35 — 35 — 50 — 65
ns
5— 5— 5 — 5—5
0—
0—
0 — 0—0 —
ns
12 — 15 — 20 — 20 — 20 —
ns
— 40 — 50 — 60 — 80 — 120 ns
— 30 — 35 — 35 — 55 — 100 ns
NOTES:
2689 tbl 11
1. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages.
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY ^(2,3,4)
ADDR’A’
tWC
MATCH
tWP
W R/ ’A’
DATAIN’A’
ADDR’B’
(1)
tAPS
tDW
tDH
VALID
MATCH
BUSY’B’
tBDA
tBDD
DATAOUT’B’
tWDD
NOTES:
tDDD
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
VALID
2689 drw 12
6.01
9