7130SA55P Datasheet, PDF (6/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE⁽³⁾
7130X20⁽²⁾ 7130X25⁽⁵⁾ 7130X35
7140X25⁽⁵⁾ 7140X35
7130X55
7140X55
7130X100
7140X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
tHZ
tPU
tPD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time^(1,4)
Output High-Z Time^(1,4)
Chip Enable to Power Up Time⁽⁴⁾
Chip Disable to Power Down Time⁽⁴⁾
20 —
— 20
— 20
11
3—
0—
— 10
0—
— 20
25 — 35
— 25 —
— 25 —
— 12 —
3—3
0—0
— 10 —
0—0
— 25 —
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP package.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
— 55
35 —
35 —
20 —
—3
—5
15 —
—0
35 —
— 100 — ns
55 — 100 ns
55 — 100 ns
25 — 40 ns
— 10 — ns
— 5 — ns
25 — 40 ns
— 0 — ns
50 — 50 ns
2689 tbl 09
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE⁽¹⁾
ADDRESS
tAA
tOH
DATAOUT
BUSYOUT
PREVIOUS DATA VALID
tRC
tOH
DATA VALID
tBDD ^(2,3)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the
address location. For simultaneous read operations, BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
2689 drw 08
6.01
6