7130SA55P Datasheet, PDF (11/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE⁽²⁾
7130X20⁽¹⁾
7130X25⁽³⁾
7140X25⁽³⁾
7130X35
7140X35
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
Interrupt Timing
tAS
Address Set-up Time
0
—
0
—
0—
tWR
Write Recovery Time
0
—
0
—
0—
tINS
Interrupt Set Time
—
20
—
25
— 25
tINR
Interrupt Reset Time
—
20
—
25
— 25
NOTES:
1. 0°C to +70°C temperature range only, PLCC and TQFP packages.
2. “X” in part numbers indicates power rating (SA or LA).
3. Not available in DIP packages .
8M824S25
7130X55
7140X55
Min. Max.
0
—
0
—
—
45
—
45
8M824S308M824S35
7130X100
7140X100
Min. Max. Unit
0
—
ns
0
—
ns
—
60
ns
—
60
ns
2689 tbl 12
TIMING WAVEFORM OF INTERRUPT MODE
INT SET:
ADDR'A'
W R/ 'A'
INT'B'
tWC
INTERRUPT ADDRESS⁽²⁾
tAS ⁽³⁾
tWR⁽⁴⁾
tINS ⁽³⁾
INT CLEAR:
ADDR'B'
OE'B'
INT'B'
tRC
INTERRUPT CLEAR ADDRESS
tAS ⁽³⁾
tINR ⁽³⁾
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
2689 drw 16
2689 drw 17
6.01
11