7130SA55P Datasheet, PDF (4/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE^(1,6) (VCC = 5.0V ± 10%)
Symbol
Parameter
Test Conditions
7130X20⁽²⁾ 7130X25⁽³⁾ 7130X35 7130X55 7130X100
7140X25⁽³⁾ 7140X35 7140X55 7140X100
Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
ICC Dynamic Operating CEL and CER = VIL, MIL. SA — — 110 280 110 230 110 190 110 190 mA
Current (Both Ports Outputs open,
LA — — 110 220 110 170 110 140 110 140
Active)
f = fMAX⁽⁴⁾
COM'L. SA 110 250 110 220 110 165 110 155 110 155
LA 110 200 110 170 110 120 110 110 110 110
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH, MIL. SA — — 30 80 25 80 20 65 20 65 mA
f = fMAX⁽⁴⁾
LA — — 30 60 25 60 20 45 20 45
COM'L. SA 30 65 30 65 25 65 20 65 20 55
LA 30 45 30 45 25 45 20 35 20 35
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH ⁽⁷⁾
MIL. SA
LA
Active Port Outputs COM'L. SA
Open, f = fMAX⁽⁴⁾
LA
— — 65 160
— — 65 125
65 165 65 150
65 125 65 115
50 150
50 115
50 125
50 90
40 125 40 125 mA
40 90 40 90
40 110 40 110
40 75 40 75
ISB3 Full Standby Current CEL and
MIL. SA — — 1.0 30 1.0 30 1.0 30 1.0 30 mA
(Both Ports - All
CER > VCC -0.2V,
LA — — 0.2 10 0.2 10 0.2 10 0.2 10
CMOS Level Inputs VIN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15 1.0 15 1.0 15 1.0 15
VIN < 0.2V,f = 0⁽⁵⁾
LA 0.2 5 0.2 5 0.2 4 0.2 4 0.2 4
ISB4 Full Standby Current CE"A" < 0.2V and MIL. SA — — 60 155 45 145 40 110 40 110 mA
(One Port - All
CE"B" > VCC -0.2V⁽⁷⁾
LA — — 60 115 45 105 40 85 40 80
CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA 60 155 60 145 45 110 40 100 40 95
VIN < 0.2V,
LA 60 115 60 105 45 85 40 70 40 70
Active Port Outputs
Open, f = fMAX⁽⁴⁾
NOTES:
2689 tbl 06
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.
3. Not available in DIP packages.
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DATA RETENTION CHARACTERISTICS (LA Version Only)
Symbol
VDR
ICCDR
tCDR(3)
tR(3)
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
Test Conditions
VCC = 2.0V, CE > VCC -0.2V
Mil.
Com’l.
VIN > VCC -0.2V or VIN < 0.2V
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
lDT7130LA/IDT7140LA
Min.
Typ.⁽¹⁾
Max.
2.0
—
—
—
100
4000
—
100
1500
0
—
—
tRC⁽²⁾
—
—
Unit
V
µA
µA
ns
ns
2689 tbl 07
6.01
4