7130SA55P Datasheet, PDF (12/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I — NON-CONTENTION
READ/WRITE CONTROL⁽⁴⁾
Left or Right Port⁽¹⁾
W R/ CE OE D0–7
Function
XH X
Z Port Disabled and in Power-
Down Mode, ISB2 or ISB4
XH X
Z
CER = CEL = VIH, Power-Down
Mode, ISB1 or ISB3
L L X DATAIN Data on Port Written Into Memory⁽²⁾
HL
L DATAOUT Data in Memory Output on Port⁽³⁾
HL H
Z High Impedance Outputs
NOTES:
2689 tbl 13
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
TABLE II — INTERRUPT FLAG^(1,4)
R/WL
L
X
X
X
Left Port
CEL OEL
L
X
X
X
X
X
L
L
A9L – A0L
3FF
X
X
3FE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
INTL
X
X
L⁽³⁾
H⁽²⁾
R/WR
X
X
L
X
Right Port
CER OER A9L – A0R
X
X
X
L
L
3FF
L
X
3FE
X
X
X
INTR
L⁽²⁾
H⁽³⁾
X
X
TABLE III — ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A9L
CEL CER A0R-A9R BUSYL(1) BUSYR(1)
Function
X
X NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
L
L
MATCH
(2)
H
Normal
(2)
Write Inhibit⁽³⁾
NOTES:
2689 tbl 15
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are
inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain,
not push-pull outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can
not be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving Low regard-
less of actual logic level on the pin.
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2689 tbl 14
6.01
12