7130SA55P Datasheet, PDF (10/14 Pages) Integrated Device Technology – HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TIMING WAVEFORM OF WRITE WITH BUSY⁽³⁾
MILITARY AND COMMERCIAL TEMPERATURE RANGES
W R/ 'A'
BUSY'B'
W R/ 'B'
tWP
tWB
(2)
tWH^{( 1 )}
2689 drw 13
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING ⁽¹⁾
ADDR
'A' AND 'B'
ADDRESSES MATCH
CE'B'
CE'A'
BUSY'A'
tAPS⁽²⁾
tBAC
tBDC
2689 drw 14
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING ⁽¹⁾
tRC OR tWC
ADDR'A'
(2)
tAPS
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
ADDR'B'
tBAA
tBDA
BUSY'B'
2689 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be
asserted (7130 only).
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