ICS9FG104 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: PLL Frequency Control Register
Byte 11
Pin #
Name
Control Function
Bit 7
-
PLL N Div7
Bit 6
-
PLL N Div6
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
N Divider Programming
Byte11 bit(7:0) and Byte10
bit(7:6)
Bit 1
-
PLL N Div1
Bit 0
-
PLL N Div0
Type
0
1
RW
RW The decimal representation of M
RW ^{and N Divider in Byte 11 and 12 will}
RW ^{configure the PLL VCO frequency.}
Default at power up = latch-in or
RW _{Byte 0 Rom table. VCO Frequency}
RW
= 14.318 x [NDiv(9:0)+8] /
RW
[MDiv(5:0)+2]
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 12
Pin #
Name
Control Function
Bit 7
-
PLL SSP7
Bit 6
-
PLL SSP6
Bit 5
-
PLL SSP5
Bit 4
-
Bit 3
-
PLL SSP4
PLL SSP3
Spread Spectrum
Programming bit(7:0)
Bit 2
-
PLL SSP2
Bit 1
-
PLL SSP1
Bit 0
-
PLL SSP0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
PWD
X
X
X
X
X
X
X
X
SMBus Table: PLL Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Bit 7
-
Reserved
Bit 6
-
PLL SSP14
Bit 5
-
PLL SSP13
Bit 4
-
Bit 3
-
Bit 2
-
PLL SSP12
PLL SSP11
PLL SSP10
Spread Spectrum
Programming bit(14:8)
Bit 1
-
PLL SSP9
Bit 0
-
PLL SSP8
Type
RW
RW
RW
RW
RW
RW
RW
0
1
These Spread Spectrum bits in
Byte 13 and 14 will program the
spread pecentage of PLL
PWD
0
X
X
X
X
X
X
X
SMBus Table: Reserved Test Register
Byte 14
Pin #
Name
Control Function
Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Reserved Test Register. Do not write to this register, erratic device operation may occur.
Bit 2
-
Bit 1
-
Bit 0
-
PWD
1
0
0
0
0
0
0
0
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
8
ICS9FG104 REV K 04/12/07