ICS9FG104 Datasheet, PDF (14/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Alternative termination for LVDS and other common differential signals. Figure 3.
Vdiff
Vp-p Vcm R1
0.45 v
0.22v 1.08 33
0.58
0.28 0.6
33
0.80
0.40 0.6
33
0.60
0.3
1.2
33
R1a = R1b = R1
R2
R3
R4
150 100
100
78.7 137
100
78.7 none 100
174 140
100
Note
ICS874003i-02 input compatible
Standard LVDS
Figure_3.
L1
L2
R3
R1a
L4
L4’
L1’
L2’
R1b
R2a R2b
HSCL Output
Buffer
L3’ L3
R2a = R2b = R2
Cable connected AC coupled application, figure 4
Component Value
Note
R5a,R5b
8.2K 5%
R6a,R6b
Cc
1K 5%
0.1 uF
Vcm
0.350 volts
3.3 Volts
R4
Down Device
REF_CLK Input
L4
L4’
Figure_4.
R5a R5b
Cc
Cc
R6a
R6b
PCIe Device
REF_CLK Input
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
14
ICS9FG104 REV K 04/12/07