ICS9FG104 Datasheet, PDF (3/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
FS2**
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
16
SPREAD**
17
SEL14M_25M#*
18
DIF_1#
19
DIF_1
20
GND
21
VDD
22
DIF_0#
23
DIF_0
24
FS1**
25
FS0**
26
IREF
27
GNDA
28
VDDA
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
PWR
PWR
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin.
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up resistor, to enable
spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
3.3V Frequency select latched input pin.
3.3V Frequency select latched input pin.
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
ICS9FG104 REV K 04/12/07