ICS9FG104 Datasheet, PDF (11/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2Ω, R_P=49.9Ω, Ι _REF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN
Output Impedance
Zo¹
V_O = V_x
3000
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single
ended signal using oscilloscope
math function.
660
-150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
-300
250
TYP MAX
850
150
1150
550
UNITS
Ω
mV
mV
mV
Crossing Voltage (var)
d-Vcross Crossing variation over all edges
140
mV
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
400MHz nominal
2.4993
2.5008 ns
400MHz spread
2.4993
2.5133 ns
333.33MHz nominal
2.9991
3.0009 ns
333.33MHz spread
2.9991
3.016
ns
266.66MHz nominal
3.7489
3.7511 ns
266.66MHz spread
3.7489
3.77
ns
Average period
Tperiod
200MHz nominal
200MHz spread
4.9985
4.9985
5.0015 ns
5.0266 ns
166.66MHz nominal
5.9982
6.0018 ns
166.66MHz spread
5.9982
6.0320 ns
133.33MHz nominal
7.4978
7.5023 ns
133.33MHz spread
7.4978
5.4000 ns
100.00MHz nominal
9.9970
10.0030 ns
100.00MHz spread
9.9970
10.0533 ns
400MHz nominal/spread
2.4143
ns
333.33MHz nominal/spread 2.9141
ns
266.66MHz nominal/spread 3.6639
ns
Absolute min period
T_absmin
200MHz nominal/spread
4.8735
ns
166.66MHz nominal/spread 5.8732
ns
133.33MHz nominal/spread 7.3728
ns
100.00MHz nominal/spread 9.8720
ns
Rise Time
t_r
V_OL = 0.175V, V_OH = 0.525V
175
700
ps
Fall Time
t_f
V_OH = 0.525V V_OL = 0.175V
175
700
ps
Rise Time Variation
d-t_r
125
ps
Fall Time Variation
d-t_f
Duty Cycle
d_t3
Measured Differentially
45
Skew, output to output
t_sk3
V_T = 50%
Jitter, PCI-e SRC phase
t_{jPCI-ephase14}
22MHz/1.5MHz/1.5MHz/10ns,
14.31818 MHz REF Clock
125
ps
55
%
35
ps
42
ps
Jitter, PCI-e SRC phase
t_{jPCI-ephase25}
22MHz/1.5MHz/1.5MHz/10ns,
25 MHz REF Clock
39
ps
Jitter, Cycle to cycle
t_jcyc-cyc
Measured Differentially
50
ps
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
or 25 MHz
3 _{Figures are for down spread.}
4 _{This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit}
http://www.pcisig.com for additional details
5 _{+/- 150 ppm for 100 MHz outputs}
NOTES
1
1
1
1
1
1
1
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
4
4
4
1
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104 REV K 04/12/07
11