ICS9FG104 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Reserved Register
Byte 7
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control Function
Type
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: Reserved Register
Byte 8
Pin #
Name
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control Function
Type
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: M/N Programming Enable
Byte 9
Pin #
Name
Bit 7
-
M/N_Enable
Bit 6
-
Bit 5
5
REFOUT_En
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Control Function
Type
M/N Prog. Enable
RW
Reserved
REFOUT Enable
RW
Reserved
Reserved
Reserved
Reserved
Reserved
0
Disable
Disable
1
Enable
Enable
PWD
0
1
1
0
0
0
0
0
SMBus Table: PLL Frequency Control Register
Byte 10
Pin #
Name
Control Function
Bit 7
-
PLL N Div8
N Divider Prog bit 8
Bit 6
-
PLL N Div9
N Divider Prog bit 9
Bit 5
-
PLL M Div5
Bit 4
-
PLL M Div4
Bit 3
-
Bit 2
-
PLL M Div3
PLL M Div2
M Divider Programming
bit (5:0)
Bit 1
-
PLL M Div1
Bit 0
-
PLL M Div0
Type
0
1
RW
RW The decimal representation of M
RW ^{and N Divider in Byte 11 and 12 will}
RW ^{configure the PLL VCO frequency.}
Default at power up = latch-in or
RW _{Byte 0 Rom table. VCO Frequency}
RW
= 14.318 x [NDiv(9:0)+8] /
RW
[MDiv(5:0)+2]
RW
PWD
X
X
X
X
X
X
X
X
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
ICS9FG104 REV K 04/12/07