ICS9FG104 Datasheet, PDF (5/17 Pages) Integrated Circuit Systems – Programmable FTG for Differential P4TM CPU, PCI-Express & SATA Clocks

ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
SMBus Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Byte 0
Pin #
Name
Control Function
Type
0
1
Bit 7
17
FS3¹
RW
Bit 6
6
Bit 5
24
FS2¹
FS1¹
RW See Frequency Selection Table,
RW
Page 1
Bit 4
25
FS0¹
RW
Bit 3
16
Spread Enable¹
RW
Off
On
Bit 2
-
Enable Software Control of Frequency, Spread Enable
(Spread Type always Software Control)
RW Hardware Select Software Select
PWD
Pin 17
Pin 6
Pin 24
Pin 25
Pin 16
0
Bit 1
Bit 0
DIF_STOP# drive mode
SPREAD TYPE
RW
Driven
RW
Down
Hi-Z
0
Center
0
Notes:
1. These bits reflect the state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
Bit 7
-
Bit 6
-
DIF_3 EN
Bit 5
-
DIF_2 EN
Bit 4
-
Bit 3
-
Bit 2
-
DIF_1 EN
Bit 1
-
DIF_0 EN
Bit 0
-
Control Function
Reserved
Output Enable
Output Enable
Reserved
Reserved
Output Enable
Output Enable
Reserved
Type
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Stop Control Register
Byte 2
Pin #
Name
Control Function
Bit 7
-
Reserved
Bit 6
-
DIF_3 STOP EN
Free Run/ Stop Enable
Bit 5
-
DIF_2 STOP EN
Free Run/ Stop Enable
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
DIF_1 STOP EN
Free Run/ Stop Enable
Bit 1
-
DIF_0 STOP EN
Free Run/ Stop Enable
Bit 0
-
Reserved
Type
RW
RW
RW
RW
0
Free-run
Free-run
Free-run
Free-run
1
Stop-able
Stop-able
Stop-able
Stop-able
PWD
0
0
0
0
0
0
0
0
IDT^TM/ICS^TM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
5
ICS9FG104 REV K 04/12/07