ICS9ERS3165 Datasheet, PDF (8/27 Pages) Integrated Device Technology – Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
40 SRCT_LR11/CR#_H
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request
control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
I/O space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
41 SRCT_LR10
42 SRCC_LR10
43 VDDSRCI/O
44 CPU_STOP#
45 PCI_STOP#
46 VDDSRC
47 SRCC_LR6
48 SRCT_LR6
49 GNDSRC
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR 1.05V to 3.3V from external power supply
IN
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3
bits are shifted in from the ICH to set the FSC, FSB, FSA values
IN
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits
are shifted in from the ICH to set the FSC, FSB, FSA values
PWR VDD pin for SRC Pre-drivers, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
PWR Ground for SRC clocks
50 SRCC_LR7/CR#_E
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request
control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
I/O . After the SRC output is disabled (high-Z), the pin can then be set to serve as a
Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
51 SRCT_LR7/CR#_F
52 VDDSRCI/O
53 CPUC_ITP_LR2/SRCC8
54 CPUT_ITP_LR2/SRCT8
55 NC
56 VDDCPU_IO
57 CPUC_F_LR1
58 CPUT_F_LR1
59 GNDCPU
60 CPUC_LR0
61 CPUT_LR0
62 VDDCPU
63 CK_PWRGD/PD#
64 FSLB/TEST_MODE
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request
control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
I/O After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
PWR 1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential
SRC pair. The function of this pin is determined by the latched input value on pin 14,
OUT
PCIF5/ITP_EN on powerup. The function is as follows:
Pin 14 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 14, PCIF5/ITP_EN
OUT
on powerup. The function is as follows:
Pin 14 latched input Value
0 = SRC8
1 = ITP
N/A No Connect
PWR 1.05V to 3.3V from external power supply
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-
running during iAMT.
OUT
True clock of low power differential CPU clock pair. This clock will be free-running
during iAMT.
PWR Ground Pin for CPU Outputs
OUT Complement clock of low power differential CPU clock pair.
OUT True clock of low power differential CPU clock pair.
PWR Power Supply 3.3V nominal.
IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical
IN
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
IDT^® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
8
1613C—02/08/12