ICS9ERS3165 Datasheet, PDF (14/27 Pages) Integrated Device Technology – Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Electrical Characteristics - Differential Jitter Parameters
PARAMETER
Symbol
Conditions
Min
Jitter, Phase
t_jphasePLL
t_jphaseLo
PCIe Gen 1
PCIe Gen 2
10kHz < f < 1.5MHz
t_{j phas eHi gh}
PCIe Gen 2
1.5MHz < f < Nyquist (50MHz)
*TA = -40 - 85°C; Supply Voltage VDD = 3.3 V +/-5%, Rs= 0Ω, CL = 2pF
TYP
Max
Units
Notes
86 ps (p-p) 1,11
3
ps
(RMS)
1,11
3.1
ps
(RMS)
1,11
Notes on Electrical Characteristics:
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Slew rate measured through Vswing centered around differential zero}
3 _{Vxabs is defined as the voltage where CLK = CLK#}
4 _{Only applies to the differential rising edge (CLK rising and CLK# falling)}
5 _{Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and}
falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The
average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz}
7 _{Operation under these conditions is neither implied, nor guaranteed.}
8 _{Maximum input voltage is not to exceed maximum VDD}
9 _{See PCI Clock-to-Clock Delay Figure}
10 _{At nominal voltage and temperature}
11 _{See http://www.pcisig.com for complete specs}
IDT^® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
14
1613C—02/08/12