ICS9ERS3165 Datasheet, PDF (20/27 Pages) Integrated Device Technology – Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 6 Clock Request Enable/Configuration Register
Bit
Name
Description
7
CR#_E_EN
Enable CR#_E (clk req) for SRC6
6
CR#_F_EN
Enable CR#_F (clk req) for SRC8
5
CR#_G_EN
Enable CR#_G (clk req) for SRC9
4
CR#_H_EN
Enable CR#_H (clk req) for SRC10
3
Reserved
Reserved
2
Reserved
Reserved
1
LCD/SRC1_STP_CRTL•
If set, LCD_SS/SRC1 stops with PCI_STOP#
0
SRC0_STP_CRTL
If set, SRC0 stop with PCI_STOP#
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Disable CR#_H
-
-
Free Running
Free Running
1
Enable CR#_E
Enable CR#_F
Enable CR#_G
Enable CR#_H
-
-
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Default
0
0
0
0
0
0
0
0
Byte 7 Vendor ID/ Revision ID Register
Bit
Name
7
Rev Code Bit 3
6
Rev Code Bit 2
5
Rev Code Bit 1
4
Rev Code Bit 0
3
Vendor ID bit 3
2
Vendor ID bit 2
1
Vendor ID bit 1
0
Vendor ID bit 0
Description
Revision ID
Vendor ID
ICS is 0001, binary
Type
R
R
R
R
R
R
R
R
0
1
Vendor specific
Default
0
0
0
1
0
0
0
1
Byte 8 Device ID & Output Enable Register
Bit
Name
Description
7
Device_ID3
6
Device_ID2
Table of Device identifier codes, used for differentiating between
5
Device_ID1
CK505 package options, etc.
4
Device_ID0
3
Reserved
Reserved
2
Reserved
Reserved
1
27MHz_nonSS/SE1_OE
0
27MHz_SS/SE2_OE
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
0
1
See Device ID Table 4
-
-
Disabled
Disabled
-
-
Enabled
Enabled
Default (TSSOP)
0
0
0
1
0
0
1
1
Default (MLF)
0
0
0
0
0
0
1
1
Byte 9 Test and Output Control Register
Bit
Name
Description
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of PCI_STOP#
6
TME_Readback
5
Reserved
4
Test Mode Select
3
Test Mode Entry
2
CPU IO_VOUT2
1
CPU IO_VOUT1
0
CPU IO_VOUT0
Truested Mode Enable (TME) strap status
Reserved
Allows test select, ignores REF/FSC/TestSel
Allows entry into test mode, ignores FSB/TestMode
CPU IO Output Voltage Select (Most Significant Bit)
CPU IO Output Voltage Select
CPU IO Output Voltage Select (Least Significant Bit)
Type
RW
R
RW
RW
RW
RW
RW
RW
0
Free running
normal operation
-
Outputs HI-Z
Normal operation
1
Stops with PCI_STOP#
assertion
no overclocking
-
Outputs = REF/N
Test mode
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
TME latch
1
0
0
1
0
1
Byte 10 Output Control Register
Bit
Name
7
27_SEL Latch Readback
6
PCI4 STOP EN
5
PCI3 STOP EN
4
PCI2 STOP EN
3
PCI1 STOP EN
2
PCI0 STOP EN
1
CPU1 Stop Enable
0
CPU0 Stop Enable
Description
Readback of 27_Select latch
Allows control of PCI4 with assertion of PCI_STOP#
Allows control of PCI3 with assertion of PCI_STOP#
Allows control of PCI2 with assertion of PCI_STOP#
Allows control of PCI1 with assertion of PCI_STOP#
Allows control of PCI0 with assertion of PCI_STOP#
Enables control of CPU1 with CPU_STOP#
Enables control of CPU0 with CPU_STOP#
Type
R
RW
0
Dot96/ LCD_SS /SE
Free running
RW
Free running
RW
Free running
RW
Free running
RW
Free running
RW
Free Running
RW
Free Running
1
SRC0/ 27MHz
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stops with PCI_STOP#
assertion
Stoppable
Stoppable
Default
27_SEL latch
1
1
1
1
1
1
1
Byte 11 iAMT/CPU2 Control Register
Bit
Name
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
CPU2_AMT_EN
2
CPU1_AMT_EN
1
Reserved
0
CPU2 Stop Enable
Description
Reserved
Reserved
Reserved
Reserved
M1 mode clk enable, only if ITP_EN=1
M1 mode clk enable
Reserved
Enables control of CPU2 with CPU_STOP#
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
Disable
Disable
-
Free Running
1
-
-
-
-
Enable
Enable
-
Stoppable
Default
0
0
0
0
0
1
0
1
IDT^® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
20
1613C—02/08/12