ICS9ERS3165 Datasheet, PDF (19/27 Pages) Integrated Device Technology – Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
Byte 0 FS Readback & PLL Selection Register
Bit
Name
Description
7
FSLC
CPU Freq. Sel. Bit (Most Significant)
6
FSLB
CPU Freq. Sel. Bit
5
FSLA
CPU Freq. Sel. Bit (Least Significant)
Type
R
R
R
0
1
See Table 1 : CPU Frequency Select Table
4
iAMT_EN
Set via SMBus or dynamically by CK505 if detects dynamic M1 R
Legacy Mode
iAMT Enabled
3
Reserved
2
SRC_Main_SEL
1
SATA_SEL
Reserved
Select source for SRC Main
Select source for SATA clock
RW
RW SRC Main = PLL5
RW SATA = SRC_Main
SRC Main = PLL2
SATA = PLL3
1 = on Power Down de-assert return to last known state
0
PD_Restore
0 = clear all SMBus configurations as if cold power-on and go to
latches open state
RW Configuration Not Saved
Configuration Saved
This bit is ignored and treated at '1' if device is in iAMT mode.
Default
Latch
Latch
Latch
iAMT power on
status
0
0
0
1
Byte 1 PLL1 Quick Config Register
Note 1 : When 27_Select pin = 0, B1b7 PWD = 1; When 27_Select pin = 1, PWD = 0
Bit
Name
7
SRC0_SEL
6
PLL5_SSC_SEL
5
PLL2_SSC SEL
4
PLL1_CF3
3
PLL1_CF2
2
PLL1_CF1
1
PLL1_CF0
0
PCI_SEL
Description
Select SRC0 or DOT96
Select 0.5% down or center SSC
Select 0.5% center or down SSC
PLL1 Quick Config Bit 3
PLL1 Quick Config Bit 2
PLL1 Quick Config Bit 1
PLL1 Quick Config Bit 0
PCI_SEL
Byte 2 Single Ended Output Enable Register
Bit
Name
7
REF_OE
6
USB_OE
5
PCIF5_OE
4
PCI4_OE
3
PCI3_OE
2
PCI2_OE
1
PCI1_OE
0
PCI0_OE
Description
Output enable for REF
Output enable for USB
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Byte 3 SRC Output Enable Register
Bit
Name
7
SRC11_OE
6
SRC10_OE
5
SRC9_OE
4
SRC8/ITP_OE
3
SRC7_OE
2
SRC6_OE
1
Reserved
0
SRC4_OE
Description
Output enable for SRC11
Output enable for SRC10
Output enable for SRC9
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Reserved
Output enable for SRC4
Byte 4 SRC/CPU/DOT Output Enable & Spread Spectrum Disable Register
Bit
Name
Description
7
SRC3_OE
Output enable for SRC3
6
SATA/SRC2_OE
Output enable for SATA/SRC2
5
SRC1_OE
Output enable for SRC1
4
SRC0/DOT96_OE
Output enable for SRC0/DOT96
3
CPU1_OE
Output enable for CPU1
2
CPU0_OE
Output enable for CPU0
1
PLL5_SSC_ON
Enable PLL5's spread modulation
0
PLL2_SSC_ON
Enable PLL2's spread modulation
Byte 5 Clock Request Enable/Configuration Register
Bit
Name
Description
7
CR#_A_EN
Enable CR#_A (clk req) for SRC0 or SRC2
6
CR#_A_SEL
Sets CR#_A to control either SRC0 or SRC2
5
CR#_B_EN
Enable CR#_B (clk req) for SRC1 or SRC4
4
CR#_B_SEL
Sets CR#_B to control either SRC1 or SRC4
3
CR#_C_EN
Enable CR#_C (clk req) for SRC0 or SRC2
2
CR#_C_SEL
Sets CR#_C to control either SRC0 or SRC2
1
CR#_D_EN
Enable CR#_D (clk req) for SRC1 or SRC4
0
CR#_D_SEL
Sets CR#_D to control either SRC1 or SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
Down
1
DOT96
Center spread
Center
See Table 2: pin 27FIX/LCDT/SRCT_LR1/SE1,
27SS/LCDC/SRCC_LR1/SE2 Configuration
Only applies if Byte 0, bit 2 = 0.
PCI from PLL5
PCI from SRC_MAIN
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
-
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
-
Output Enabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable CR#_A
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
Default
Note 1
0
0
0
0
1
0
1
Default
1
1
1
1
1
1
1
1
Default
1
1
1
1
1
1
1
1
Default
1
1
1
1
1
1
1
1
Default
0
0
0
0
0
0
0
0
IDT^® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
19
1613C—02/08/12