ICS9ERS3165 Datasheet, PDF (2/27 Pages) Integrated Device Technology – Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock

ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
TSSOP Pin Description
Pin# Pin Name
1 PCI0/CR#_A
2 VDDPCI
3 PCI1/CR#_B
4 PCI2/TME
5 PCI3
6 PCI4/27_SEL
7 PCI5_F/ITP_EN
8 GNDPCI
9 VDD48
10 USB48M/FSLA
11 GND48
12 VDDI/O96MHz
13 DOT96T/SRCT_LR0
14 DOT96C/SRCC_LR0
15 GND
16 VDD
Type DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock
Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using
I/O
the CR#_A_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled.
Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
PWR Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock
Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this
pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1
of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using
I/O
the CR#_B_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled.
Byte 5, bit 4 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is
sampled on power-up as follows
I/O 0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
OUT 3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the
I/O logic value on this pin determines the power-up default of DOT_96/SRC0 and
27MHz/SRC1 output and the function table for the pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not
affected by the state of the PCI_STOP# pin. On powerup, the state of this pin
I/O determines whether pins 46 and 47 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
PWR Ground for PCI clocks.
PWR Power supply for USB clock, nominal 3.3V.
I/O
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
PWR Ground pin for the 48MHz outputs.
PWR 1.05V to 3.3V from external power supply
OUT
True clock of SRC or DOT96. The power-up default function depends on
27_Select,1= SRC0, 0=DOT96
OUT
Complement clock of SRC or DOT96. The power-up default function depends
on 27_Select,1= SRC0, 0=DOT96
PWR Ground pin for the DOT96 clocks.
PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
IDT^® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
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1613C—02/08/12