ICS87972I Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE
6.
CRYSTAL
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Parameter
Test Conditions
Minimum Typical Maximum
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Fundamental
10
25
50
Shunt Capacitance
7
Drive Level
1
Units
MHz
Ω
pF
mW
TABLE 7. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
÷2
125
MHz
÷4
f
Output Frequency
MAX
÷6
120
MHz
80
MHz
÷8
60
MHz
t(Ø)
Static Phase Offset; ^CLK0
NOTE 1
CLK1
QFB ÷ 8
In Frequency = 50MHz
-270
-330
130
70
530
ps
470
ps
tsk(o) Output Skew; NOTE 2, 4
550
ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
±100
ps
f_VCO
t_LOCK
t_R / t_F
PLL VCO Lock Range
PLL Lock Time; NOTE 3
Output Rise/Fall Time;
NOTE 3
200
0.8V to 2V
0.15
480
MHz
10
ms
1.2
ns
t_PW
Output Pulse Width
t_PERIOD/2 - 750 t_PERIOD/2 ± 500 t_PERIOD/2 + 750
ps
t_PZL, t_PZH Output Enable Time; NOTE 3
10
ns
t_PLZ, t_PHZ Output Disable TIme; NOTE 3
8
ns
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
87972DYI
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REV. E JUNE 25, 2010