ICS87972I Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS87972I is a low skew, LVCMOS/LVTTL Clock
Generator. The ICS87972I has three selectable inputs
and provides fourteen LVCMOS/LVTTL outputs.
FEATURES
• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs; (12) clocks,
(1) feedback, (1) sync
The ICS87972I is a highly flexible device. Using the crystal
oscillator input, it can be used to generate clocks for a
system. All of these clocks can be the same frequency or
the device can be configured to generate up to three
different frequencies among the three output banks. Using
one of the single ended inputs, the ICS87972I can be
used as a zero delay buffer/multiplier/divider in clock
distribution applications.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-
input frequency ratios. In addition, 2 outputs in Bank C (QC2,
QC3) can be selected to be inverting or non-inverting.
The output frequency range is 8.33MHz to125MHz. Input
frequency range is 5MHz to 120MHz.
• Selectable crystal oscillator interface or LVCMOS/LVTTL
reference clock inputs
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 480MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard andd lead-free RoHS-compliant
packages
The ICS87972I also has a QSYNC output which can be used
for system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period of the faster clock
prior to coincident rising edges of Bank A and Bank C clocks.
QSYNC then goes high again when the coincident rising
edges of Bank A and Bank C occur. This feature is used
primarily in applications where Bank A and Bank C are
running at different frequencies, and is particularly useful
when they are running at non-integer multiples of one
another.
Example Applications:
1. System Clock generator: Use a 16.66MHz Crystal to
generate eight 33.33MHz copies for PCI and four
100MHz copies for the CPU or PCI-X.
2. Line Card Multiplier: Multiply 19.44MHz from a back
plane to 77.76MHz for the line Card ASICs and Serdes.
3. Zero Delay buffer for Synchronous memory: Fan out up
to twelve 100MHz copies from a memory controller ref-
erence clock to the memory chips on a memory module
with zero delay.
• Compatible with PowerPC™andPentium™ Microprocessors
PIN ASSIGNMENT
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
VDDO
QA2
GNDO
QA1
VDDO
QA0
GNDO
VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
25
42
24
43
23
44
22
45
21
46
ICS87972I
20
47
19
48
18
49
17
50
16
51
15
52
14
1 2 3 4 5 6 7 8 9 10 11 12 13
FSEL_FB1
QSYNC
GNDO
QC0
VDDO
QC1
FSEL_C0
FSEL_C1
QC2
VDDO
QC3
GNDO
INV_CLK
87972DYI
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
www.idt.com
1
REV. E JUNE 25, 2010