ICS87972I Datasheet, PDF (4/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1
2
3
4
5, 26, 27
6
7
8
9, 10
11, 12
13
14
15, 24, 30,
35, 39, 47, 51
16, 18, 21, 23
17, 22, 33
37, 45, 49
19, 20
25
28
29
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
REF_SEL
CLK_SEL
CLK0, CLK1
XTAL1,
XTAL2
V_DDA
INV_CLK
Type
Description
Power
Power supply ground.
Input
Pullup
Active HIGH Master Reset. Active LOW output enable. When logic
HIGH, the internal dividers are reset and the outputs are in high
impedance (Hi-Z). When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Input
Pullup
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
Input
Pullup
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
Input
Input
Input
Input
Pullup
Pullup
Pullup
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and
reference clocks. LVCMOS / LVTTL interface levels.
Selects between crystal and reference clock. When LOW, selects
CLK0 or CLK1. When HIGH, selects crystal inputs.
LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK0.
When HIGH, selects CLK1. LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Power
Input
Analog supply pin.
Pullup
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
GNDO
Power
Power supply ground.
QC3, QC2,
QC1, QC0
Output
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
V_DDO
FSEL_C1,
FSEL_C0
QSYNC
V_DD
QFB
Power
Output supply pins.
Input Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Output
Power
Synchronization output for Bank A and Bank C. Refer to Figure 1,
Timing Diagrams. LVCMOS / LVTTL interface levels.
Core supply pins.
Output
Feedback clock output. LVCMOS / LVTTL interface levels.
31
EXT_FB Input Pullup External feedback. LVCMOS / LVTTL interface levels.
32, 34, 36, 38
40, 41
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
Output
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
42, 43
44, 46, 48, 50
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Output
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
52
VCO_SEL
Input
Pullup
Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects
VCO ÷ 2. LVCMOS / LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See table 2, Pin Characteristics, for typical values.
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REV. E JUNE 25, 2010